1. Technical Field of the Invention
The present invention relates to a volatile memory cell circuit, and particularly to a memory cell circuit for a static random access memory device.
2. Background of the Invention
Static random access memory (SRAM) devices have been employed for decades to store electronic data. An SRAM device includes an array of memory cells organized into rows and columns of memory cells. An addressable word line is coupled to the memory cells in a distinct row of memory cells. The memory cells in a column of memory cells are coupled to an addressable pair of bit lines. Data is written to and read from a memory cell in the memory cell array by selecting a row of memory cells and accessing memory cells therein that are coupled to selected bit line pairs. The organization and operation of SRAM devices are well known in the art.
The conventional SRAM cell is a six transistor (6T) cell. Specifically, the SRAM includes a latch element formed by a pair of cross coupled inverters. The latch element stores a single bit of data, with the value of the data bit depending upon the state of the latch element. The conventional SRAM cell includes a pair of transmission or pass gate transistors coupled to the input of the cross-coupled inverters. The pass gate transistors provide access to the SRAM for reading and writing data. The 6T SRAM cell is well known in the art.
Over the years, attempts have been made to optimize the SRAM cell. Improvements have occurred primarily with respect to memory cell layout and/or fabrication techniques. Little changes, however, have been directed to reducing the circuit itself so as to reduce fabrication complexity.
The present invention is directed towards reducing the circuitry within the SRAM cell. According to an embodiment of the present invention, the SRAM cell is a four transistor (4T) cell including a first and a second pull-down transistor. A first transmission or pass gate transistor has a first source/drain terminal connected to a first bit line of a bit line pair and a second source/drain terminal connected to the drain terminal of the first pull-down transistor and the gate terminal of the second pull-down transistor. A second transmission or pass gate transistor has a first source/drain terminal connected to a second bit line of the bit line pair and a second source/drain terminal connected to the drain terminal of the second pull-down transistor and the gate terminal of the first pull-down transistor. The gate terminal of the first and second transmission gate transistors is connected to a word line of the SRAM device. The first and second pull-down transistors are bulk transistors having source/drain regions formed in a semiconductor substrate. The first and second transmission gate transistors are thin film transistors. The memory cell is without pull-up transistors that are typically coupled to the pull-down transistors in conventional SRAM cell designs.
In order for the SRAM cell to maintain data, the first and second transmission gate transistors produce a subthreshold current that flows from the bit lines (tied to a high reference voltage level when the memory cell is not being accessed) and through the first and second transmission gate transistors to the first and second pull-down transistor. The amount of subthreshold current is sized by setting the threshold voltage of the first and second transmission gate transistors so that the drain terminal of the pull-down transistor that is turned off is pulled to a voltage level representing a logic high level. In this way, the memory cell performs a latching function in remaining in one of two latched states, thus preserving the data bit value represented thereby.
The fabrication of the SRAM includes initially forming first and second bulk transistors, each of the first and second bulk transistors including drain/source regions defined in a semiconductor substrate and a gate region. Next and/or as part of the steps involved with forming the bulk transistors, the first and second thin film transistors are formed over the semiconductor substrate. Each of the first and second thin film transistors including gate, drain and source regions, so that the drain region of the first thin film transistor is connected to the drain region of the first bulk transistor and the gate region of the second bulk transistor, and the drain region of the second thin film transistor is connected to the drain region of the second bulk transistor and the gate region of the first bulk transistor. Next, the threshold voltage of the first and second thin film transistors are set so that a subthreshold current of the first thin film transistor is capable of maintaining the drain region of the first bulk transistor at a logic high level when the first bulk transistor is turned off, and a subthreshold leakage current of the second thin film transistor is capable of maintaining the drain region of the second bulk transistor at a logic high level when the second bulk transistor is turned off.